Invention Grant
- Patent Title: Digital phase controlled delay circuit
- Patent Title (中): 数字相控延时电路
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Application No.: US14577245Application Date: 2014-12-19
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Publication No.: US09369136B1Publication Date: 2016-06-14
- Inventor: Viacheslav Suetinov , Hans Joakim Bangs , Philip Hackney
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Green, Howard & Mughal LLP
- Main IPC: G11C7/00
- IPC: G11C7/00 ; H03L7/08 ; G11C7/22 ; G11C7/10
Abstract:
An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from the DLL. Both the DLL and phase adjustor may be formed from current starved delay elements that are biased from a common bias generator circuit.
Public/Granted literature
- US20160182061A1 DIGITAL PHASE CONTROLLED DELAY CIRCUIT Public/Granted day:2016-06-23
Information query
