Invention Grant
US09378960B2 Method and structure for improved floating gate oxide integrity in floating gate semiconductor devices 有权
浮栅半导体器件中浮栅氧化物完整性的改进方法和结构

  • Patent Title: Method and structure for improved floating gate oxide integrity in floating gate semiconductor devices
  • Patent Title (中): 浮栅半导体器件中浮栅氧化物完整性的改进方法和结构
  • Application No.: US13092043
    Application Date: 2011-04-21
  • Publication No.: US09378960B2
    Publication Date: 2016-06-28
  • Inventor: Yihguei Wey
  • Applicant: Yihguei Wey
  • Applicant Address: US WA Camas
  • Assignee: WAFERTECH, LLC
  • Current Assignee: WAFERTECH, LLC
  • Current Assignee Address: US WA Camas
  • Agency: Duane Morris LLP
  • Main IPC: H01L21/336
  • IPC: H01L21/336 H01L21/28 H01L29/423
Method and structure for improved floating gate oxide integrity in floating gate semiconductor devices
Abstract:
Methods for forming floating gate transistors provide for using a self-aligned plug formed over a floating gate electrode without use of an additional photolithography operation. The plug is centrally disposed and is formed and aligned using spacers. The spacers are formed alongside edges of a patterned sacrificial, oxidation resistant layer that includes an opening that defines the floating gate region. The plug may be formed of a silicon material and which becomes oxidized along with the floating gate such that the plug eventually forms part of the floating gate electrode or the plug may be formed of a nitride or other oxidation resistant material to retard or prevent oxidation in the central portion of the floating gate in which the plug is aligned.
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