Invention Grant
- Patent Title: Method for forming interconnects
- Patent Title (中): 形成互连的方法
-
Application No.: US14677673Application Date: 2015-04-02
-
Publication No.: US09378976B2Publication Date: 2016-06-28
- Inventor: Roey Shaviv
- Applicant: APPLIED Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: APPLIED Materials, Inc.
- Current Assignee: APPLIED Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Christensen O'Connor Johnson Kindness PLLC
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/44 ; H01L23/52 ; H01L21/311 ; H01L21/768 ; H01L21/321 ; H01L23/522 ; H01L23/532

Abstract:
A conductive interconnect including trenches (110) and (186) and vias (202) are formed in a workpiece (100) by applying a dielectric film stack (120) over the workpiece, and thereafter applying photoresist (140) over the film stack. Trenches (142) are patterned in the photoresist, wherein the trenches are in segments disposed end-to-end to each other. The segments are longitudinally spaced apart from each other at locations where the vias (202) are to be located. The trenches are etched into the dielectric film stack, and then filled with conductive material to form metal line segments (186). Vias (192) are patterned in the gaps separating the adjacent ends of the longitudinally-related lines (186). The patterned vias are etched and then filled with a conductive material, with the ends of the adjacent line segments (186) serving to accurately locate the vias, in a direction along the lengths of the trenches.
Public/Granted literature
- US20150287675A1 METHOD FOR FORMING INTERCONNECTS Public/Granted day:2015-10-08
Information query
IPC分类: