Invention Grant
- Patent Title: Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon
-
Application No.: US14820669Application Date: 2015-08-07
-
Publication No.: US09379204B2Publication Date: 2016-06-28
- Inventor: Keith E. Fogel , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Otterstedt, Ellenbogen & Kammer, LLP
- Agent Daniel P Morris
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/02 ; H01L21/308 ; H01L21/762 ; H01L21/8252

Abstract:
A structure having application to electronic devices includes a III-V layer having high crystal quality and a low defect density on a lattice mismatched substrate. Trenches are formed in a layer of III-V semiconductor material grown on a substrate having a different lattice constant. Dielectric material is deposited within the trenches, forming dielectric regions. A portion of the layer of III-V material is removed, leaving new trenches defined by the dielectric regions. A new layer of III-V semiconductor material having reduced defect density is grown on the remaining portion of the originally deposited III-V semiconductor layer and within the trenches defined by the dielectric regions.
Public/Granted literature
- US20160126335A1 LATTICE MATCHED ASPECT RATIO TRAPPING TO REDUCE DEFECTS IN III-V LAYER DIRECTLY GROWN ON SILICON Public/Granted day:2016-05-05
Information query
IPC分类: