Invention Grant
- Patent Title: Method for forming doped areas under transistor spacers
- Patent Title (中): 在晶体管间隔物下形成掺杂区域的方法
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Application No.: US14450385Application Date: 2014-08-04
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Publication No.: US09379213B2Publication Date: 2016-06-28
- Inventor: Perrine Batude , Jean-Michel Hartmann , Benoit Sklenard , Maud Vinet
- Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT , STMICROELECTRONICS SA
- Applicant Address: FR Paris FR Montrouge
- Assignee: Commissariat a l'energie atomique et aux energies alternatives,STMICROELECTRONICS SA
- Current Assignee: Commissariat a l'energie atomique et aux energies alternatives,STMICROELECTRONICS SA
- Current Assignee Address: FR Paris FR Montrouge
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: FR1357931 20130809
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/78 ; H01L29/66 ; H01L21/02 ; H01L29/16 ; H01L29/417 ; H01L29/786 ; H01L29/161 ; H01L21/265 ; H01L21/28
Abstract:
Method for fabricating a transistor comprising the steps consisting of: forming sacrificial zones in a semi-conductor layer, either side of a transistor channel zone, forming insulating spacers on said sacrificial zones against the sides of the gate of said transistor, removing said sacrificial zones so as to form cavities, with the cavities extending on either side of said channel zone and penetrating under said spacers, forming doped semi-conductor material in said cavities, with said semi-conductor material penetrating under said spacers.
Public/Granted literature
- US20150044841A1 METHOD FOR FORMING DOPED AREAS UNDER TRANSISTOR SPACERS Public/Granted day:2015-02-12
Information query
IPC分类:
