Invention Grant
- Patent Title: Integrated circuit with state and data retention
- Patent Title (中): 具有状态和数据保持的集成电路
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Application No.: US13922649Application Date: 2013-06-20
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Publication No.: US09383802B1Publication Date: 2016-07-05
- Inventor: Jun Pin Tan , Kiun Kiet Jong
- Applicant: Altera Corporation
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G06F1/32
- IPC: G06F1/32

Abstract:
A method of operating an integrated circuit that includes a plurality of registers may include receiving a sleep mode request for the integrated circuit. The sleep mode request may be a control signal received with control circuitry on the integrated circuit. The plurality of registers may be configured to operate as a scan chain when the sleep mode request is received. Integrated circuit state information that are stored in the plurality of registers may be retrieved by operating the scan chain and stored in a memory module. The integrated circuit may be placed in a sleep mode. Placing the integrated circuit in the sleep mode may reduce power consumption of the integrated circuit.
Information query