Invention Grant
- Patent Title: Method of estimating program speed-up with highly parallel architectures
- Patent Title (中): 使用高度并行架构估计程序加速的方法
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Application No.: US14212711Application Date: 2014-03-14
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Publication No.: US09384016B2Publication Date: 2016-07-05
- Inventor: Karthikeyan Sankaralingam , Newsha Ardalani , Xiaojin Zhu
- Applicant: Wisconsin Alumni Research Foundation
- Applicant Address: US WI Madison
- Assignee: Wisconsin Alumni Research Foundation
- Current Assignee: Wisconsin Alumni Research Foundation
- Current Assignee Address: US WI Madison
- Agency: Boyle Fredrickson, S.C.
- Main IPC: G06F3/00
- IPC: G06F3/00 ; G06F19/00 ; G06F9/445 ; G06F9/54 ; G05B23/02 ; G06F9/45
Abstract:
The amount of speed-up that can be obtained by moving a program to a parallel architecture is determined by a model associating speed-up to micro-architecture independent features of the program execution. The model may be generated, for example, by linear regression, by evaluating programs that have been ported to parallel architectures where the micro-architecture independent features are known.
Public/Granted literature
- US20150261536A1 METHOD OF ESTIMATING PROGRAM SPEED-UP WITH HIGHLY PARALLEL ARCHITECTURES Public/Granted day:2015-09-17
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