Invention Grant
- Patent Title: Global timing modeling within a local context
- Patent Title (中): 本地环境下的全局时序建模
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Application No.: US12783915Application Date: 2010-05-20
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Publication No.: US09384309B2Publication Date: 2016-07-05
- Inventor: Mahesh A. Iyer , Amir H. Mottaez , Rajnish K. Prasad
- Applicant: Mahesh A. Iyer , Amir H. Mottaez , Rajnish K. Prasad
- Applicant Address: US CA Mountain View
- Assignee: SYNOPSYS, INC.
- Current Assignee: SYNOPSYS, INC.
- Current Assignee Address: US CA Mountain View
- Agency: Park, Vaughan, Fleming & Dowler LLP
- Agent Laxman Sahasrabuddhe
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Some embodiments of the present invention provide techniques and systems for determining and using margin values. An arrival time at an output pin of a logic gate can be determined. Next, required times at the output pin of the logic gate can be determined. Each required time can be associated with a timing end-point in a path-group, affected by that pin. The system can then determine a first set of slack values at the output pin of the logic gate by computing a difference between the required times and the arrival time. Next, the system can determine a set of margin values at the output pin of the logic gate by computing a difference between the first set of slack values and a second set of slack values at the timing end-points in the path-groups. Next, the system can use the set of margin values to optimize the logic gate.
Public/Granted literature
- US20110289464A1 GLOBAL TIMING MODELING WITHIN A LOCAL CONTEXT Public/Granted day:2011-11-24
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