Typical hybrid graphics systems operate in either a “high-performance mode” or in an “energy saver mode.” While operating in the high-performance mode, a discrete graphics processing unit (dGPU) performs high-performance graphics processing operations and also receives and satisfies access requests targeting a configuration space within the dGPU. While operating in the energy saver mode, an integrated graphics processing unit (iGPU) performs graphics processing operations and the dGPU is powered down. In this scenario, a system management unit (SMU) intercepts and satisfies access requests targeting the dGPU. Since access requests targeting the dGPU are satisfied while the dGPU is powered down, the dGPU continues to be enumerated in the system using the same system resources as originally granted, and can therefore be switched to for implementing high-performance mode more quickly than if it was removed, and required a complete plug-and-play re-enumeration and re-allocation of system resources.