A memory device includes a memory array comprising memory cells, sense amplifiers configured to sense data stored in the memory cells of the memory array, and control circuitry configured to generate a plurality of separate sense amplifier control signals for application to respective control inputs of respective ones of the sense amplifiers. For example, the memory device may comprise a row of dummy memory cells each coupled to a dummy wordline. In such an arrangement, the control circuitry may comprise a plurality of logic gates coupled to respective ones of the dummy memory cells, with each such logic gate configured to generate a corresponding one of the separate sense amplifier control signals for a corresponding one of the sense amplifiers as a function of a data transition at a bitline of the corresponding dummy memory cell. The separate sense amplifier control signals may comprise respective sense amplifier enable signals.