Invention Grant
- Patent Title: Semiconductor device
- Patent Title (中): 半导体器件
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Application No.: US14836868Application Date: 2015-08-26
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Publication No.: US09384852B1Publication Date: 2016-07-05
- Inventor: Atsushi Kawasumi
- Applicant: KABUSHIKI KAISHA TOSHIBA
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Patterson & Sheridan, LLP
- Priority: JP2015-049260 20150312
- Main IPC: G11C17/00
- IPC: G11C17/00 ; G11C17/18 ; G11C17/16 ; H01L27/22 ; H01L27/112 ; G11C29/00

Abstract:
A semiconductor device which includes a normal cell, a replica cell, a word line, a first bit line, a bias generation circuit, a second bit line, and a current generation circuit. The normal cell is a one-time programmable (OTP) type memory cell. The replica cell has characteristics equivalent to those of the normal cell. The word line is electrically connected in common to a control terminal of the normal cell and a control terminal of the replica cell. The first bit line is electrically connected to an input-output terminal of the replica cell. The bias generation circuit is electrically connected to the first bit line. The second bit line is electrically connected to an input-output terminal of the normal cell. The current generation circuit is electrically connected to the second bit line. The bias generation circuit and the current generation circuit are controlled through a common control line.
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