Invention Grant
- Patent Title: Method for insulating singulated electronic die
- Patent Title (中): 隔离单片电子模具的方法
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Application No.: US14469478Application Date: 2014-08-26
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Publication No.: US09385041B2Publication Date: 2016-07-05
- Inventor: Francis J. Carney
- Applicant: Semiconductor Components Industries, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Agent Kevin B. Jackson
- Main IPC: H01L21/78
- IPC: H01L21/78 ; H01L25/00 ; H01L23/498

Abstract:
In one embodiment, a method of forming an electronic device includes providing a wafer having plurality of die separated by spaces. The method includes plasma singulating the wafer through the spaces to form singulation lines that expose side surfaces of the plurality of die. The method includes forming an insulating layer on the exposed side surfaces. In one embodiment, the steps of singulating and forming the insulating layer are carried out with the wafer mounted to a carrier substrate that supports the wafer and singulated die during both steps.
Public/Granted literature
- US20160064282A1 METHOD FOR INSULATING SINGULATED ELECTRONIC DIE AND STRUCTURE Public/Granted day:2016-03-03
Information query
IPC分类: