- Patent Title: Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
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Application No.: US14747372Application Date: 2015-06-23
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Publication No.: US09385047B2Publication Date: 2016-07-05
- Inventor: Dalong Zhao , Pushkar Ranade , Bruce McWilliams
- Applicant: Mie Fujitsu Semiconductor Limited
- Applicant Address: JP Kuwana, Mie
- Assignee: Mie Fujitsu Semiconductor Limited
- Current Assignee: Mie Fujitsu Semiconductor Limited
- Current Assignee Address: JP Kuwana, Mie
- Agency: Baker Botts L.L.P.
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/8238 ; H01L21/82 ; H01L21/02
Abstract:
Semiconductor manufacturing processes include forming conventional channel field effect transistors (FETs) and deeply depleted channel (DDC) FETs on the same substrate and selectively forming a plurality of gate stack types where those different gate stack types are assigned to and formed in connection with one or more of a conventional channel NFET, a conventional channel PFET, a DDC-NFET, and a DDC-PFET in accordance a with a predetermined pattern.
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