Invention Grant
- Patent Title: Chip diode and diode package
- Patent Title (中): 芯片二极管和二极管封装
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Application No.: US14703928Application Date: 2015-05-05
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Publication No.: US09385093B2Publication Date: 2016-07-05
- Inventor: Hiroki Yamamoto
- Applicant: ROHM CO., LTD.
- Applicant Address: JP Kyoto
- Assignee: Rohm Co., Ltd.
- Current Assignee: Rohm Co., Ltd.
- Current Assignee Address: JP Kyoto
- Agency: Rabin & Berdo, P.C.
- Priority: JP2011-227964 20111017; JP2011-270253 20111209; JP2012-060557 20120316; JP2012-060558 20120316; JP2012-060559 20120316; JP2012-086784 20120405; JP2012-148862 20120702; JP2012-149732 20120703; JP2012-149733 20120703; JP2012-149734 20120703; JP2012-217882 20120928
- Main IPC: H01L31/109
- IPC: H01L31/109 ; H01L31/112 ; H01L29/00 ; H01L23/00 ; H01L23/495 ; H01L23/522 ; H01L29/861 ; H01L29/866 ; H01L29/872 ; H01L49/02 ; H01L27/06 ; H01L23/544 ; H01L29/417 ; H01L27/102 ; H01L29/06 ; H01L23/31 ; H01L27/02
Abstract:
A chip diode includes a plurality of diode cells formed on a semiconductor substrate, each having a diode junction region; and parallel connection portions provided on the substrate to connect the diode cells in parallel and including a first electrode formed in one side of the substrate and having at least two extending portions extending only to another side of the substrate. At least two diode junction regions are formed along each of the extending portions. At least two extending portions are formed to have line symmetry and at least four diode junction regions are formed to have point symmetry and line symmetry in a plane view. A space is formed in the center of at least the four diode junction regions. Fluctuations in characteristics of the diode are suppressed even when a large stress is applied to a pad of a diode package for electrical connection with the exterior.
Public/Granted literature
- US20150249055A1 CHIP DIODE AND DIODE PACKAGE Public/Granted day:2015-09-03
Information query
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