Invention Grant
- Patent Title: 3D semiconductor package interposer with die cavity
- Patent Title (中): 具有模腔的3D半导体封装插入器
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Application No.: US14249637Application Date: 2014-04-10
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Publication No.: US09385095B2Publication Date: 2016-07-05
- Inventor: Shin-Puu Jeng , Shang-Yun Hou , Kim Hong Chen , Wensen Hung , Szu-Po Huang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/00 ; H01L23/13 ; H01L23/498 ; H01L25/00 ; H01L23/538 ; H01L21/683 ; H01L25/065 ; H01L25/18 ; H01L21/56 ; H01L23/367 ; H01L23/42 ; H01L23/31

Abstract:
Disclosed herein is a method of forming a device, comprising mounting a plurality of first interconnects on one or more first integrated circuit dies. One or more second integrated circuit dies are mounted on a first side of an interposer. The interposer is mounted to at a second side to the first integrated circuit dies, the plurality of first interconnects disposed outside of the interposer. The interposer is mounted to a first side of a substrate by attaching the first interconnects to the substrate, the substrate in signal communication with one or more of the first integrated circuit dies through the first interconnects.
Public/Granted literature
- US20140217610A1 3D Semiconductor Package Interposer with Die Cavity Public/Granted day:2014-08-07
Information query
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