Invention Grant
US09385106B1 Method for providing charge protection to one or more dies during formation of a stacked silicon device
有权
在堆叠硅器件形成期间向一个或多个管芯提供电荷保护的方法
- Patent Title: Method for providing charge protection to one or more dies during formation of a stacked silicon device
- Patent Title (中): 在堆叠硅器件形成期间向一个或多个管芯提供电荷保护的方法
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Application No.: US14444661Application Date: 2014-07-28
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Publication No.: US09385106B1Publication Date: 2016-07-05
- Inventor: Raghunandan Chaware , Inderjit Singh , Glenn O'Rourke , Ganesh Hariharan
- Applicant: Xilinx, Inc.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agent Gerald Chan
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/00 ; H01L21/56 ; H01L21/304 ; H01L23/60
Abstract:
A method for providing charge protection to a die during formation of an integrated circuit, includes bonding the die to an interposer to form an unprotected stacked silicon component; encapsulating the unprotected stacked silicon component with a mold compound to cover at least a top surface of the die; grinding the mold compound to reduce a thickness of the mold compound; bonding a carrier wafer to the mold compound; removing the carrier wafer from the mold compound; and removing the mold compound from the top surface of the die after the carrier wafer is removed from the mold compound, to expose the top surface of the die.
Information query
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