Invention Grant
- Patent Title: Parallel bit interleaver
- Patent Title (中): 并行位交织器
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Application No.: US14825389Application Date: 2015-08-13
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Publication No.: US09385755B2Publication Date: 2016-07-05
- Inventor: Mihail Petrov
- Applicant: Panasonic Corporation
- Applicant Address: JP Osaka
- Assignee: PANASONIC CORPORATION
- Current Assignee: PANASONIC CORPORATION
- Current Assignee Address: JP Osaka
- Agency: Wenderoth, Lind & Ponack, L.L.P.
- Priority: EP11004124 20110518
- Main IPC: H03M13/00
- IPC: H03M13/00 ; H03M13/11 ; H04L1/00 ; H03M13/25 ; H03M13/27 ; H03M13/29 ; H03M13/35

Abstract:
A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N/M folding sections, each of the constellation words being associated with one of the F×N/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.
Public/Granted literature
- US20150349799A1 PARALLEL BIT INTERLEAVER Public/Granted day:2015-12-03
Information query
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