A correction phase locked loop (CPLL), including a signal processing unit that receives a digitized input signal from a satellite, the signal processing unit comprising (a) a primary correlator and primary discriminator, connected in series and generating a main error signal Z1 from the digitized input signal; (b) a correction correlator and a correction discriminator connected in series and generating a correction signal Z2; and (c) an adder for adding the main error signal Z1 and the correction signal Z2 to produce a common error signal Z. A loop filter filters the common error signal Z to produce a corrected error signal that is used for frequency-phase control of a Numerical Control Oscillator (NCO). The NCO generates two mutually orthogonal output reference signals whose phase is substantially free of multipath errors.