A fractional PLL circuit includes a phase comparator, a voltage-controlled oscillation unit, a phase-selection unit equally dividing a period of an output-clock signal output from the voltage-controlled oscillation unit into a predetermined number of phases, selecting one of the phases, and generating a phase-shift clock signal having a rising edge in the selected phase, a frequency-divider unit dividing a frequency of the phase-shift clock signal and outputting the divided signal to the phase comparator, and a phase-control unit determining the phase to be selected for changing a duration of a period of the phase-shift clock signal by a predetermined phase-shift amount and controlling the phase-selection unit. The phase-control unit operates with the frequency-divided phase-shift clock signal.