The signal transmitting device of a signal transmitting/receiving device according to the present disclosure includes a signal processing unit that outputs a video signal as parallel data together with the first clock (the pixel clock); a first buffer memory to which the parallel data is written based on the first clock from the signal processing unit, and from which the written parallel data is read based on the second clock having a constant frequency equal to or higher than that of the first clock; and a transmitting unit. The transmitting unit receives the parallel data read from the first buffer memory and the second clock, converts the parallel data into serial data, and outputs the serial data to the signal line based on the second clock. The first buffer memory and the transmitting unit are formed of an FPGA (field-programmable gate array).