A mobile device (300) includes an oscillator (310) to generate a reference clock signal, a phase-locked loop (PLL) circuit (320) to generate a PLL output clock signal, a transceiver (330), a system-on-a-chip (SOC) (340) including a processor (342) and a number of other modules, and a control logic (350). The transceiver (330) generates a status control signal that indicates whether the transceiver (330) is in an active state or in an idle state. The control logic (350) receives the status control signal, and in response thereto, selectively enables/disables the PLL circuit (320), selectively routes either the reference clock signal or the PLL output clock signal to the processor (342) and/or the other modules of the SOC (340), and/or selectively routes either an idle clock signal or the PLL output clock signal to the transceiver (330).