- Patent Title: Memory arrays with a memory cell adjacent to a smaller size of a pillar having a greater channel length than a memory cell adjacent to a larger size of the pillar and methods
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Application No.: US14710976Application Date: 2015-05-13
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Publication No.: US09391082B2Publication Date: 2016-07-12
- Inventor: Koji Sakui , Peter Feeley
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: H01L27/115
- IPC: H01L27/115 ; G11C16/04 ; H01L29/788 ; H01L29/792 ; H01L29/66
Abstract:
The disclosure is related to memory arrays and methods. One such memory array has a substantially vertical pillar. A memory cell adjacent to the pillar where the pillar has a first size has a greater channel length than a memory cell adjacent to the pillar where the pillar has a second size larger than the first size.
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