Invention Grant
- Patent Title: Methods for packaging integrated circuits
- Patent Title (中): 集成电路封装方法
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Application No.: US14175651Application Date: 2014-02-07
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Publication No.: US09401287B2Publication Date: 2016-07-26
- Inventor: Loon Kwang Tan , Yuanlin Xie , Ping Chet Tan
- Applicant: Altera Corporation
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/48 ; H01L21/56 ; H01L21/683 ; H01L23/36 ; H01L23/31 ; H01L23/00 ; H01L23/498

Abstract:
Techniques for packaging an integrated circuit include attaching a die to a conductive layer before forming dielectric layers on an opposing surface of the conductive layer. The conductive layer may first be formed on a carrier substrate before the die is disposed on the conductive layer. The die may be electrically coupled to the conductive layer via wires or solder bumps. The carrier substrate is removed before the dielectric layers are formed. The dielectric layers may collectively form a coreless package substrate for the integrated circuit package.
Public/Granted literature
- US20150228506A1 METHODS FOR PACKAGING INTEGRATED CIRCUITS Public/Granted day:2015-08-13
Information query
IPC分类: