Invention Grant
- Patent Title: Quad flat no-lead package and manufacturing method thereof
- Patent Title (中): 四边形无铅封装及其制造方法
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Application No.: US14656631Application Date: 2015-03-12
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Publication No.: US09401318B2Publication Date: 2016-07-26
- Inventor: Chi-Jin Shih
- Applicant: ChipMOS Technologies Inc.
- Applicant Address: TW Hsinchu
- Assignee: ChipMOS Technologies Inc.
- Current Assignee: ChipMOS Technologies Inc.
- Current Assignee Address: TW Hsinchu
- Agency: Patterson & Sheridan, LLP
- Priority: TW103113159A 20140410
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/00 ; H01L21/56 ; H01L21/48 ; H01L23/31

Abstract:
A quad flat no-lead package includes an encapsulant, and a plurality of chip pads, a plurality of bond pads and a chip disposed in the encapsulant. Each chip pad is connected to at least one of the chip pads adjacent thereto by a first extending portion. The chip pads and the bond pads are arranged in an array. The chip pads are disposed at the center of the array and the bond pads are disposed around the chip pads. Each of the bond pads and at least one of the bond pads or one of the chip pads adjacent thereto each has a second extending portion formed therebetween and corresponding to each other. Every two of the second extending portions corresponding to each other are separated by a groove. The chip is mounted on a top surface of the chip pads and is electrically coupled to the bond pads.
Public/Granted literature
- US20150294925A1 QUAD FLAT NO-LEAD PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2015-10-15
Information query
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