Invention Grant
- Patent Title: Semiconductor device having an on die termination circuit
- Patent Title (中): 具有导体终端电路的半导体器件
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Application No.: US14023962Application Date: 2013-09-11
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Publication No.: US09401324B2Publication Date: 2016-07-26
- Inventor: Masaru Koyanagi , Yasuhiro Suematsu
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: H01L23/485
- IPC: H01L23/485 ; H01L23/522 ; H01L25/10 ; H01L27/02 ; H01L27/06 ; H01L25/065

Abstract:
According to one embodiment, a semiconductor device includes a transistor formed on a semiconductor chip, a lower-layer wiring connected to a diffusion layer of the transistor, and drawn outside the diffusion layer, and an upper-layer wiring drawn out from a pad electrode formed on the semiconductor chip, connected to the lower-layer wiring, and having resistivity lower than that of the lower-layer wiring.
Public/Granted literature
- US20150008582A1 SEMICONDUCTOR DEVICE Public/Granted day:2015-01-08
Information query
IPC分类: