Invention Grant
- Patent Title: Method for manufacturing semiconductor device and alignment mark of semiconductor device
- Patent Title (中): 制造半导体器件的方法和半导体器件的对准标记
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Application No.: US14197548Application Date: 2014-03-05
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Publication No.: US09401332B2Publication Date: 2016-07-26
- Inventor: Kotaro Noda
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P
- Main IPC: H01L23/544
- IPC: H01L23/544

Abstract:
According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include forming a stacked layer in a memory cell region and a mark region, forming a first mask layer above the stacked layer, and forming a second mask layer above the first mask layer; forming the second mask layer into first mask pattern features and forming a first alignment mark pattern feature; forming second mask pattern features and then removing the first mask pattern features; opening part of the second mask pattern features and forming a third mask layer having an opening; removing part of the second mask pattern features; removing the third mask layer; forming a fourth mask layer; etching the first mask layer; removing the fourth mask layer and then removing the second mask pattern features; and etching the stacked layer.
Public/Granted literature
- US20150145150A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND ALIGNMENT MARK OF SEMICONDUCTOR DEVICE Public/Granted day:2015-05-28
Information query
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