Invention Grant
- Patent Title: Molding structure for wafer level package
- Patent Title (中): 晶圆级封装的成型结构
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Application No.: US14222423Application Date: 2014-03-21
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Publication No.: US09401337B2Publication Date: 2016-07-26
- Inventor: Chen-Hua Yu , Chung-Shi Liu , Chih-Fan Huang , Chih-Wei Lin , Wei-Hung Lin , Ming-Da Cheng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/00 ; H01L23/31 ; H01L21/56
Abstract:
Apparatus, and methods of manufacture thereof, in which a molding compound is formed between spaced apart microelectronic devices. The molding compound comprises micro-filler elements. No boundary of any of the micro-filler elements is substantially parallel to a substantially planar surface of the molding compound, or to a substantially planar surface of any of the microelectronic devices.
Public/Granted literature
- US20150170937A1 Molding Structure for Wafer Level Package Public/Granted day:2015-06-18
Information query
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