Invention Grant
- Patent Title: Semiconductor package having wire bond wall to reduce coupling
- Patent Title (中): 半导体封装具有线接合壁以减少耦合
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Application No.: US13929688Application Date: 2013-06-27
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Publication No.: US09401342B2Publication Date: 2016-07-26
- Inventor: Shun Meen Kuo , Margaret Szymanowski , Paul Hart
- Applicant: Shun Meen Kuo , Margaret Szymanowski , Paul Hart
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Main IPC: H03F3/68
- IPC: H03F3/68 ; H03F3/195 ; H01L23/00 ; H03F1/02 ; H03F1/56 ; H03F3/24 ; H01L23/047 ; H01L23/552 ; H01L23/66 ; H01L23/24

Abstract:
A system and method for a package including a wire bond wall to reduce coupling is presented. The package includes a substrate, and a first circuit on the substrate. The first circuit includes a first electrical device, a second electrical device, and a first wire bond array interconnecting the first electrical device and the second electrical device. The package includes a second circuit on the substrate adjacent to the first circuit, the second circuit includes a second wire bond array interconnecting a third electrical device and a fourth electrical device. The package includes a wire bond wall including a plurality of wire bonds over the substrate between the first circuit and the second circuit. The wire bond wall is configured to reduce an electromagnetic coupling between the first circuit and the second circuit during an operation of at least one of the first circuit and the second circuit.
Public/Granted literature
- US20150002226A1 SEMICONDUCTOR PACKAGE HAVING WIRE BOND WALL TO REDUCE COUPLING Public/Granted day:2015-01-01
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