Invention Grant
US09401424B2 High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
有权
使用Si：C和SiGe外延源/漏极的高性能应力增强型MOSFET及其制造方法
- Patent Title: High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
- Patent Title (中): 使用Si：C和SiGe外延源/漏极的高性能应力增强型MOSFET及其制造方法
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Application No.: US14325540Application Date: 2014-07-08
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Publication No.: US09401424B2Publication Date: 2016-07-26
- Inventor: Huajie Chen , Dureseti Chidambarrao , Omer H. Dokumaci
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel & Sibley, P.A.
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/78 ; H01L21/308 ; H01L29/10 ; H01L29/66 ; H01L27/092
Abstract:
Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a stressing layer on a substrate. The method may include doping the stressing layer with dopants. The method may include forming a silicide layer on the stressing layer. Moreover, the stressing layer may include a first lattice constant different from a second lattice constant of the substrate.
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