When a current detection voltage VCS that corresponds to a voltage drop across a detection resistor RCS exceeds a first threshold value VADIM, a current limit comparator asserts a reset pulse. A zero current detection circuit generates a set pulse configured as an instruction to turn on a switching transistor. A logic circuit generates an output pulse S14 according to the reset pulse and the set pulse. When the current detection signal VCS exceeds a second threshold value VTH, a second comparator asserts a comparison signal. An abnormal state detection period is set to a first time period from a time point at which the switching transistor turns on. When the comparison signal is asserted in the abnormal state detection period, an abnormal state detection circuit judges that an abnormal state has occurred.