In order to provide a circuit arrangement (100) and also a method for clock and/or data recovery (CDR) having low power consumption, having low power loss and also having scalability of the power loss from the clock and/or data recovery at the data rate, at least one frequency regulation circuit and at least one phase regulation circuit are proposed, wherein firstly only the frequency regulation circuit is active for the purpose of setting the frequency on the basis of the data rate that can be applied to the data input and then changeover to the phase regulation circuit occurs for the purpose of ascertaining the phase difference between the data input and the clock input.