Invention Grant
- Patent Title: Circuit and method for monolithic stacked integrated circuit testing
- Patent Title (中): 单片堆叠集成电路测试电路及方法
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Application No.: US14828174Application Date: 2015-08-17
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Publication No.: US09404971B2Publication Date: 2016-08-02
- Inventor: Sandeep Kumar Goel , Ashok Mehta
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G01R31/3177 ; G01R31/3185
Abstract:
A monolithic stacked integrated circuit (IC) is provided with a known-good-layer (KGL) test circuit. The KGL test circuit includes a scan segment, and a plurality of inputs, outputs, and multiplexers coupled to the scan segment. The KGL test circuit further includes a plurality of control elements such that scan testing of the stacked IC may be conducted on a layer-by-layer basis.
Public/Granted literature
- US20150355277A1 Circuit And Method For Monolithic Stacked Integrated Circuit Testing Public/Granted day:2015-12-10
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