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US09405881B2 Cycle accurate state analysis with programmable trigger logic 有权
使用可编程触发逻辑循环准确状态分析

Cycle accurate state analysis with programmable trigger logic
Abstract:
In one embodiment, cycle-accurate information may be collected by stopping an input clock associated with a functional block of a SoC using a programmable trigger signal. The programmable trigger signal may also stops a root clock of the SoC. Cycle-accurate information may be collected regarding the functional block and at least one other functional block of the SoC at the time of the programmable trigger signal. The collected information may be outputted and used to debug the SoC in a time-efficient manner.
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