Invention Grant
- Patent Title: Cycle accurate state analysis with programmable trigger logic
- Patent Title (中): 使用可编程触发逻辑循环准确状态分析
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Application No.: US14577804Application Date: 2014-12-19
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Publication No.: US09405881B2Publication Date: 2016-08-02
- Inventor: Subhra Sundar Bandyopadhyay , Jayanth Sankar Mekkoth
- Applicant: Cisco Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: CISCO TECHNOLOGY, INC.
- Current Assignee: CISCO TECHNOLOGY, INC.
- Current Assignee Address: US CA San Jose
- Agency: Patterson & Sheridan, LLP
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F17/50

Abstract:
In one embodiment, cycle-accurate information may be collected by stopping an input clock associated with a functional block of a SoC using a programmable trigger signal. The programmable trigger signal may also stops a root clock of the SoC. Cycle-accurate information may be collected regarding the functional block and at least one other functional block of the SoC at the time of the programmable trigger signal. The collected information may be outputted and used to debug the SoC in a time-efficient manner.
Public/Granted literature
- US20160180006A1 CYCLE ACCURATE STATE ANALYSIS WITH PROGRAMMABLE TRIGGER LOGIC Public/Granted day:2016-06-23
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