A static timing analysis method for input/output modes of an integrated circuit design, that includes loading the integrated circuit design described in a hardware description language into a memory. An active zone for static timing analysis is defined, which comprises logic and interconnect between an input/output port and a selected level of sequential logic elements upstream from an input port and downstream from an output port. A description of the active zone is generated using the hardware description language. Then a static timing analysis is performed on the logic of the active zone.