A memory array includes an array of memory cells. The memory array further includes at least two read tracking cells in a read tracking column. The memory array further includes a read tracking circuit coupled to the at least two read tracking cells, wherein the read tracking circuit is configured to generate a global tracking result signal based on outputs from the at least two read tracking cells. The memory array further includes memory control circuitry, wherein the memory control circuitry is configured to reset a memory clock based on the global tracking result signal.