Invention Grant
- Patent Title: Decreasing the critical dimensions in integrated circuits
- Patent Title (中): 降低集成电路的关键尺寸
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Application No.: US14977146Application Date: 2015-12-21
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Publication No.: US09406503B2Publication Date: 2016-08-02
- Inventor: Efrain Altamirano Sanchez , Farrukh Qayyum Yasin , Raven Demeyer
- Applicant: IMEC VZW , Katholieke Universiteit Leuven, KU LEUVEN R&D
- Applicant Address: BE Leuven BE Leuven
- Assignee: IMEC VZW,Katholieke Universiteit Leuven, KU LEUVEN R&D
- Current Assignee: IMEC VZW,Katholieke Universiteit Leuven, KU LEUVEN R&D
- Current Assignee Address: BE Leuven BE Leuven
- Agency: McDonnell Boehnen Hulbert & Berghoff LLP
- Priority: EP14199520 20141219
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/02 ; H01L21/311 ; H01L21/324 ; H01L21/027 ; H01L29/06
Abstract:
A method for lithographic patterning of a substrate is described. The method comprises obtaining a substrate to be patterned. It further comprises subsequently performing at least twice the following cycle: applying a lithographical patterning process of a thermally shrinkable metal-oxide layer for forming a metal-oxide pattern, and thermally shrinking the metal-oxide pattern. The different metal oxide patterns formed during the at least two cycles are positioned in proximity to each other such that the shrunk metal-oxide patterns form together an overall pattern to be transferred to the substrate. After performing the cycle at least twice, the overall pattern is transferred to the substrate.
Public/Granted literature
- US20160181090A1 Decreasing the Critical Dimensions in Integrated Circuits Public/Granted day:2016-06-23
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