Invention Grant
US09406506B2 Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon
有权
晶格匹配的纵横比捕获,以减少在硅上直接生长的III-V层的缺陷
- Patent Title: Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon
- Patent Title (中): 晶格匹配的纵横比捕获,以减少在硅上直接生长的III-V层的缺陷
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Application No.: US14534131Application Date: 2014-11-05
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Publication No.: US09406506B2Publication Date: 2016-08-02
- Inventor: Keith E. Fogel , Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Otterstedt, Ellenbogen & Krammer, LLP
- Agent Daniel P. Morris
- Main IPC: H01L21/02
- IPC: H01L21/02 ; H01L29/20 ; H01L29/06

Abstract:
A structure having application to electronic devices includes a III-V layer having high crystal quality and a low defect density on a lattice mismatched substrate. Trenches are formed in a layer of III-V semiconductor material grown on a substrate having a different lattice constant. Dielectric material is deposited within the trenches, forming dielectric regions. A portion of the layer of III-V material is removed, leaving new trenches defined by the dielectric regions. A new layer of III-V semiconductor material having reduced defect density is grown on the remaining portion of the originally deposited III-V semiconductor layer and within the trenches defined by the dielectric regions.
Public/Granted literature
- US20160126094A1 LATTICE MATCHED ASPECT RATIO TRAPPING TO REDUCE DEFECTS IN III-V LAYER DIRECTLY GROWN ON SILICON Public/Granted day:2016-05-05
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