Invention Grant
US09406506B2 Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon 有权
晶格匹配的纵横比捕获,以减少在硅上直接生长的III-V层的缺陷

Lattice matched aspect ratio trapping to reduce defects in III-V layer directly grown on silicon
Abstract:
A structure having application to electronic devices includes a III-V layer having high crystal quality and a low defect density on a lattice mismatched substrate. Trenches are formed in a layer of III-V semiconductor material grown on a substrate having a different lattice constant. Dielectric material is deposited within the trenches, forming dielectric regions. A portion of the layer of III-V material is removed, leaving new trenches defined by the dielectric regions. A new layer of III-V semiconductor material having reduced defect density is grown on the remaining portion of the originally deposited III-V semiconductor layer and within the trenches defined by the dielectric regions.
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