Invention Grant
US09406578B2 Chip package having extended depression for electrical connection and method of manufacturing the same 有权
用于电连接的具有延迟凹陷的芯片封装及其制造方法

Chip package having extended depression for electrical connection and method of manufacturing the same
Abstract:
A semiconductor package includes a semiconductor chip, a first and a second depression, a first and second redistribution layer and a packaging layer. The semiconductor chip has an electronic component and a conductive pad that are electrically connected and disposed on an upper surface of the semiconductor chip. The first depression and first redistribution layer extend from the upper surface toward the lower surface of the semiconductor chip. The first redistribution layer and the conductive pad are electrically connected. The second depression and the second redistribution layer extends from the lower surface toward the upper surface and is in connection with the first depression through a connection portion. The second redistribution layer is electrically connected to the first redistribution layer through the connection portion. The packaging layer is disposed on the lower surface.
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