Invention Grant
- Patent Title: Chip package having extended depression for electrical connection and method of manufacturing the same
- Patent Title (中): 用于电连接的具有延迟凹陷的芯片封装及其制造方法
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Application No.: US14638219Application Date: 2015-03-04
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Publication No.: US09406578B2Publication Date: 2016-08-02
- Inventor: Ying-Nan Wen , Chien-Hung Liu , Ho-Yin Yiu
- Applicant: XINTEC INC.
- Applicant Address: TW Taoyuan
- Assignee: XINTEC INC.
- Current Assignee: XINTEC INC.
- Current Assignee Address: TW Taoyuan
- Agency: Liu & Liu
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/44 ; H01L23/31 ; H01L21/268 ; H01L21/3105 ; H01L21/56 ; H01L21/768 ; H01L23/00

Abstract:
A semiconductor package includes a semiconductor chip, a first and a second depression, a first and second redistribution layer and a packaging layer. The semiconductor chip has an electronic component and a conductive pad that are electrically connected and disposed on an upper surface of the semiconductor chip. The first depression and first redistribution layer extend from the upper surface toward the lower surface of the semiconductor chip. The first redistribution layer and the conductive pad are electrically connected. The second depression and the second redistribution layer extends from the lower surface toward the upper surface and is in connection with the first depression through a connection portion. The second redistribution layer is electrically connected to the first redistribution layer through the connection portion. The packaging layer is disposed on the lower surface.
Public/Granted literature
- US20150255358A1 CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2015-09-10
Information query
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