Invention Grant
- Patent Title: Latch-up immunity nLDMOS
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Application No.: US14696986Application Date: 2015-04-27
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Publication No.: US09406667B2Publication Date: 2016-08-02
- Inventor: Da-Wei Lai
- Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Current Assignee Address: SG Singapore
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: H01L29/94
- IPC: H01L29/94 ; H01L27/02 ; H01L29/78 ; H01L29/06 ; H01L29/49 ; H01L29/08 ; H01L29/417 ; H01L29/66

Abstract:
An improved nLDMOS ESD protection device having an increased holding voltage is disclosed. Embodiments include: providing in a substrate a DVNW region; providing a HVPW region in the DVNW region; providing bulk and source regions in the HVPW region; providing a drain region in the DVNW region, separate from the HVPW region; and providing a polysilicon gate over a portion of the HVPW region and the DVNW region.
Public/Granted literature
- US20150236006A1 NOVEL LATCH-UP IMMUNITY NLDMOS Public/Granted day:2015-08-20
Information query
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