Invention Grant
US09406669B2 Method and structure for vertical tunneling field effect transistor and planar devices
有权
垂直隧道场效应晶体管和平面器件的方法和结构
- Patent Title: Method and structure for vertical tunneling field effect transistor and planar devices
- Patent Title (中): 垂直隧道场效应晶体管和平面器件的方法和结构
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Application No.: US13794481Application Date: 2013-03-11
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Publication No.: US09406669B2Publication Date: 2016-08-02
- Inventor: Harry-Hak-Lay Chuang , Yi-Ren Chen , Chi-Wen Liu , Chao-Hsiung Wang , Ming Zhu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L27/06 ; H01L21/8234 ; H01L21/8238 ; H01L27/088 ; H01L27/092

Abstract:
The present disclosure provides one embodiment of a method of forming a tunnel field effect transistor (TFET). The method includes forming a semiconductor mesa on a semiconductor substrate; performing a first implantation to the semiconductor substrate and the semiconductor mesa to form a drain of a first type conductivity; forming a first dielectric layer on the semiconductor substrate and sidewall of the semiconductor mesa; forming a gate stack on the sidewall of the semiconductor mesa and the first dielectric layer; forming a second dielectric layer on the first dielectric layer and the gate stack; and forming, on the semiconductor mesa, a source having a second type conductivity opposite to the first type conductivity. The gate stack includes a gate dielectric and a gate electrode on the gate dielectric. The source, drain and gate stack are configured to form the TFET.
Public/Granted literature
- US20140252442A1 Method and Structure for Vertical Tunneling Field Effect Transistor and Planar Devices Public/Granted day:2014-09-11
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