Invention Grant
US09406695B2 Circuit and method for improving ESD tolerance and switching speed
有权
改善ESD容限和开关速度的电路和方法
- Patent Title: Circuit and method for improving ESD tolerance and switching speed
- Patent Title (中): 改善ESD容限和开关速度的电路和方法
-
Application No.: US14521378Application Date: 2014-10-22
-
Publication No.: US09406695B2Publication Date: 2016-08-02
- Inventor: Eric S. Shapiro , Matt Allison
- Applicant: Peregrine Semiconductor Corporation
- Applicant Address: US CA San Diego
- Assignee: Peregrine Semiconductor Corporation
- Current Assignee: Peregrine Semiconductor Corporation
- Current Assignee Address: US CA San Diego
- Agency: Jaquez Land Greenhaus LLP
- Agent Martin J. Jaquez, Esq.; John Land, Esq.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/82 ; H01L27/12 ; H01L27/02 ; H01L29/10
Abstract:
Embodiments of systems, methods, and apparatus for improving ESD tolerance and switching time for semiconductor devices including metal-oxide-semiconductor (MOS) field effect transistors (FETs), and particularly to MOSFETs fabricated on semiconductor-on-insulator and silicon-on-sapphire substrates. Embodiments provide an improved FET structure having an accumulated charge sink (ACS) circuit, fast switching times, and improved ESD tolerance.
Public/Granted literature
- US20150145052A1 Circuit and Method for Improving ESD Tolerance and Switching Speed Public/Granted day:2015-05-28
Information query
IPC分类:
