Invention Grant
- Patent Title: Interconnect structure for connecting dies and methods of forming the same
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Application No.: US14725163Application Date: 2015-05-29
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Publication No.: US09406712B2Publication Date: 2016-08-02
- Inventor: Shu-Ting Tsai , Dun-Nian Yaung , Jen-Cheng Liu , Shih Pei Chou , U-Ting Chen , Chia-Chieh Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, LLP
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L27/146 ; H01L25/16 ; H01L21/768 ; H01L23/522 ; H01L23/00 ; H01L27/06 ; H01L27/28 ; H01L25/065 ; H01L25/18
Abstract:
A structure includes a first chip having a first substrate, and first dielectric layers underlying the first substrate, with a first metal pad in the first dielectric layers. A second chip includes a second substrate, second dielectric layers over the second substrate and bonded to the first dielectric layers, and a second metal pad in the second dielectric layers. A conductive plug includes a first portion extending from a top surface of the first substrate to a top surface of the first metal pad, and a second portion extending from the top surface of the first metal pad to a top surface of the second metal pad. An edge of the second portion is in physical contact with a sidewall of the first metal pad. A dielectric layer spaces the first portion of the conductive plug from the first plurality of dielectric layers.
Public/Granted literature
- US20150287757A1 Interconnect Structure for Connecting Dies and Methods of Forming the Same Public/Granted day:2015-10-08
Information query
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