Invention Grant
US09406753B2 Semiconductor devices including superlattice depletion layer stack and related methods
有权
包括超晶格耗尽层堆叠和相关方法的半导体器件
- Patent Title: Semiconductor devices including superlattice depletion layer stack and related methods
- Patent Title (中): 包括超晶格耗尽层堆叠和相关方法的半导体器件
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Application No.: US14550272Application Date: 2014-11-21
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Publication No.: US09406753B2Publication Date: 2016-08-02
- Inventor: Robert Mears , Hideki Takeuchi , Erwin Trautmann
- Applicant: ATOMERA INCORPORATED
- Applicant Address: US CA Los Gatos
- Assignee: ATOMERA INCORPORATED
- Current Assignee: ATOMERA INCORPORATED
- Current Assignee Address: US CA Los Gatos
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L21/762 ; H01L29/78 ; H01L29/06 ; H01L29/15 ; H01L29/16 ; H01L21/8238 ; H01L27/092 ; H01L29/66

Abstract:
A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions.
Public/Granted literature
- US20150144878A1 SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE DEPLETION LAYER STACK AND RELATED METHODS Public/Granted day:2015-05-28
Information query
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