Invention Grant
- Patent Title: Method of manufacturing isolation structure and non-volatile memory with the isolation structure
- Patent Title (中): 隔离结构制造方法和隔离结构的非易失性存储器
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Application No.: US14691580Application Date: 2015-04-21
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Publication No.: US09406784B1Publication Date: 2016-08-02
- Inventor: Chun-Yu Chuang , Yi-Lin Hsu , Liang-Chuan Lai
- Applicant: Powerchip Technology Corporation
- Applicant Address: TW Hsinchu
- Assignee: Powerchip Technology Corporation
- Current Assignee: Powerchip Technology Corporation
- Current Assignee Address: TW Hsinchu
- Agency: Jianq Chyun IP Office
- Priority: TW104103413A 20150202
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/28 ; H01L21/283 ; H01L21/762 ; H01L27/115

Abstract:
A method of manufacturing an isolation structure suitable for a non-volatile memory is provided. A substrate is provided. A dielectric layer, a conductive layer, and a hard mask layer are sequentially formed on the substrate. The hard mask layer and the conductive layer are patterned to form a first trench which exposes the dielectric layer. A first liner is formed on the substrate. The first liner and the dielectric layer that are exposed by the first trench are removed to expose the substrate. A spacer is formed on sidewalls of the conductive layer and the hard mask layer. The substrate is partly removed to form in a second trench with use of the conductive layer and the hard mask layer with the spacer as a mask. An isolation layer is formed in the second trench. The distance between the conductive layers is greater than the width of the second trench.
Public/Granted literature
- US20160225882A1 METHOD OF MANUFACTURING ISOLATION STRUCTURE AND NON-VOLATILE MEMORY WITH THE ISOLATION STRUCTURE Public/Granted day:2016-08-04
Information query
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