A wafer level package structure for temperature sensing elements, which includes a wafer cover and a substrate. The wafer cover is formed of infrared penetrable material. The wafer cover has a plurality of package walls, and the plurality of package walls form a plurality of first grooves and a plurality of second grooves in the wafer cover. The substrate includes a plurality of chip areas, a plurality of soldering areas, and a plurality of pin areas. The plurality of chip areas are disposed a temperature sensing chip respectively and correspond to the plurality of first grooves respectively and the plurality of soldering areas solder with respect to the plurality of package walls, such that the plurality of chip areas and the plurality of first grooves form a plurality of vacuum sealed spaces respectively.