A multi-phase SMPS has N switching circuits; a setting signal generator generating a setting signal based on an output signal of the SMPS; a clock signal generator generating a system clock signal; and a controller receiving the setting signal and the system clock signal, the controller generating N shifted phase clock signals according to the system clock signal, and the N shifted phase clock signals forming loop phase clocks, and the controller further generates N switching control signals based on the setting signal and the N shifted phase clock signals.