Invention Grant
US09411014B2 Reordering or removal of test patterns for detecting faults in integrated circuit
有权
重新排列或去除用于检测集成电路故障的测试模式
- Patent Title: Reordering or removal of test patterns for detecting faults in integrated circuit
- Patent Title (中): 重新排列或去除用于检测集成电路故障的测试模式
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Application No.: US14222485Application Date: 2014-03-21
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Publication No.: US09411014B2Publication Date: 2016-08-09
- Inventor: Sushovan Podder , Parthajit Bhattacharya , Rohit Kapur
- Applicant: Synopsys, Inc.
- Applicant Address: US CA Mountain View
- Assignee: Synopsys, Inc.
- Current Assignee: Synopsys, Inc.
- Current Assignee Address: US CA Mountain View
- Agency: Fenwick & West LLP
- Priority: IN1262/CHE/2013 20130322
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G06F11/00 ; G01R31/3185 ; G01R31/3183
Abstract:
A method for reordering a test pattern set for testing an integrated circuit is disclosed. A productivity index is computed for each test pattern in a test pattern set. The productivity index of a first test pattern and the productivity index of a second test pattern are compared. If the productivity index of the second test pattern is larger than the productivity index of the first test pattern, the location of the first test pattern and the second test pattern are swapped.
Public/Granted literature
- US20140289579A1 Reordering or Removal of Test Patterns for Detecting Faults in Integrated Circuit Public/Granted day:2014-09-25
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