In an embodiment, a processor includes at least one core. The at least one core includes an execution unit and a current protection (IccP) controller. The IccP controller may receive instruction width information associated with one or more instructions of an instruction queue prior to execution of the instructions by the execution unit. The IccP controller may determine an anticipated highest current level (Icc) for the at least one core based on the instruction width information. The IccP controller may generate a request for a first license for the at least one core that is associated with the Icc. Other embodiments are described and claimed.