Invention Grant
- Patent Title: Multiprocessor system and synchronous engine device thereof
- Patent Title (中): 多处理器系统及其同步发动机装置
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Application No.: US13819886Application Date: 2011-08-30
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Publication No.: US09411778B2Publication Date: 2016-08-09
- Inventor: Ninghui Sun , Fei Chen , Zheng Cao , Kai Wang , Xuejun An
- Applicant: Ninghui Sun , Fei Chen , Zheng Cao , Kai Wang , Xuejun An
- Applicant Address: CN Beijing
- Assignee: INSTITUTE OF COMPUTING TECHNOLOGY OF THE CHINESE ACADEMY OF SCIENCES
- Current Assignee: INSTITUTE OF COMPUTING TECHNOLOGY OF THE CHINESE ACADEMY OF SCIENCES
- Current Assignee Address: CN Beijing
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner LLP
- Priority: CN201010267931 20100830
- International Application: PCT/CN2011/001458 WO 20110830
- International Announcement: WO2012/027959 WO 20120308
- Main IPC: G06F15/173
- IPC: G06F15/173 ; G06F15/76 ; G06F9/52 ; G06F9/30

Abstract:
The invention discloses a multiprocessor System and synchronous engine device thereof. the synchronous engine includes: a plurality of storage queues, wherein one of the queues stores all synchronization primitives from one of the processors; a plurality of scheduling modules, selecting the synchronization primitives for execution from the plurality of storage queues and then according to the type of the synchronization primitive transmitting the selected synchronization primitives to corresponding processing modules for processing, scheduling modules corresponding in a one-to-one relationship with the storage queues; a plurality of processing modules, receiving the transmitted synchronization primitives to execute different functions; a virtual synchronous memory structure module, using small memory space and mapping main memory spaces of all processors into a synchronization memory structure to realize the function of all synchronization primitives through a control logic; a main memory port, communicating with virtual synchronous memory structure module to read and write the main memory of all processors, and initiate an interrupt request to processors; a configuration register, storing various configuration information required by processing modules.
Public/Granted literature
- US20130166879A1 MULTIPROCESSOR SYSTEM AND SYNCHRONOUS ENGINE DEVICE THEREOF Public/Granted day:2013-06-27
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