An electronic apparatus having plural memories of different performances such as bus widths facilitates achievement of its potential as a system. The electronic apparatus has a first memory and a memory controller configured to control the first memory. Upon a second memory being detected, the memory controller compares bus widths of the first memory and the second memory with each other. Upon the bus width of the second memory being broader than the bus width of the first memory, the memory controller makes a setting such that access to the second memory precedes access to the first memory.